(1) Field of the Invention
This invention relates to a nonvolatile semiconductor memory and, more particularly, to a nonvolatile semiconductor memory, such as a flash memory, to which data can be written and in which data can be erased.
(2) Description of the Related Art
Flash memories are nonvolatile semiconductor memories in which written data can instantly be erased in the block, and are widely used at present as data stores in various apparatus, such as computers and portable terminals. A flash memory has an array structure in which many memory cells are connected by bit lines and word lines. Usually a NOR type, a NAND type, and the like are known as methods for connecting memory cells. Data is written to a memory cell selected by a bit line and a word line. Written data is read out or erased from a memory cell selected by a bit line and a word line.
A memory cell may have a structure including, for example, a stacked gate memory transistor fabricated by forming a floating gate over a semiconductor substrate in which a diffusion layer to be used as a source region and a drain region is formed with a gate insulating film between and by forming a control gate over the floating gate with an insulating film between. With such a memory cell, data is stored with an electric charge held in the floating gate located nearer the semiconductor substrate. That is to say, when voltage is applied to the control gate, the threshold of the memory cell is low if an electric charge is not held in the floating gate. The threshold of the memory cell is high if an electric charge is injected into and held in the floating gate. Accordingly, the difference in threshold between these two states is used for storing data.
A channel hot electron injection, for example, is known as a method for injecting an electric charge into the floating gate. With the channel hot electron injection, hot electrons accelerated in a channel region between the source region and the drain region by a horizontal electric field are injected into the floating gate by a gate electric field. An FN tunnel emission, for example, is known as a method for emitting an electric charge held in the floating gate. With the FN tunnel emission, by applying a positive voltage to the semiconductor substrate or applying a negative voltage to the control gate, a Fowler-Nordheim (FN) tunnel current is made to flow and an electric charge is drawn out from the floating gate.
As stated above, such flash memories are currently used in various apparatus. Not only increasing data storage capacity but also miniaturizing memory devices themselves have become important problems. For example, devising the arrangement of an array with a rise in the integration level of memory cells as a primary object is proposed to solve these problems (see Japanese Patent Laid-Open Publication No. Hei10-93057). Up to that time the method of connecting a drain region common to two memory transistors to a bit line via a contact portion had been adopted for arranging an array. According to this proposal, four memory, transistors share one source region or one drain region when an array is arranged. By doing so, an attempt to reduce the area of contact portions and to raise the integration level of memory cells is made.
With conventional general flash memories of, for example, the NOR type, structurally random access can be gained and reading is performed at a high speed. However, over-erasing and the like may occur. Accordingly, sufficient care must be devoted to the lowering of the threshold of a memory transistor. However, if the threshold is not lowered sufficiently to avoid over-erasing, then the difference in threshold between a state in which data is written to the memory transistor and a state in which data stored in the memory transistor is erased becomes small. This leads to a data write/erase error or makes high-speed reading difficult. With conventional general flash memories of the NAND type, structurally the threshold of a memory transistor can be lowered to a value obtained at the time of a floating gate being in a depletion state. However, a source region or a drain region is common to a plurality of memory transistors, so it is very difficult to read out data at a high speed.
A flash memory using not only memory transistors but also select transistors has recently been reported. FIG. 5 shows an example of a layout of a conventional flash memory using a select transistor.
FIG. 5 shows a memory cell 100 including a laminated structure which consists of a floating gate (FG) 101 and a control gate (CG) 102 and a select gate (SG) 103 adjacent to the laminated structure. The memory cells 100 are separated by a shallow trench isolation (STI) 104.
In each memory cell 100 the floating gate (FG) 101 is formed over a semiconductor substrate with an insulating film between. The control gate 102 is formed straight over the floating gates 101 formed in the memory cells 100 with an insulating film between. The select gate 103 is formed over the semiconductor substrate with an insulating film between in parallel with the control gate 102. A source line (SL) 105 and a drain region 106 are formed in the semiconductor substrate. A source contact portion 107 is connected to the source line 105 which extends parallel with the control gate 102 and the like. A bit contact portion 109 which connects with a bit line (BL) 108 at an upper layer that extends in a direction perpendicular to the control gate 102 and the like is connected to the drain region 106.
With a NOR-type flash memory not using a select transistor, the following problem arises. When written data is erased, an electric current also flows through a non-selected memory transistor if the threshold of a selected memory transistor becomes a negative voltage. This leads to a data write/erase error. By using the above select transistor, a sufficiently great difference in electric current can be secured between a state in which data is written to a memory transistor and a state in which data is erased in the memory transistor even if the threshold of the memory transistor becomes a negative voltage. As a result, data can be written/erased with accuracy and high-speed reading can be performed. However, if a select transistor is simply formed in a NOR-type flash memory, the area of each memory cell increases accordingly.